1. Technical Field
The present disclosure relates generally to a computer system having a processor, a main memory, and a cache, and more particularly to a computer system and a method for enhancing cache prefetch behavior.
2. Discussion of Related Art
A common problem in computer design is the increasing latency, in terms of processor cycles, required for transferring data or information between the processor (or processors) and the main memory of a computer system. The increasing number of processor cycles has led to ever-larger caches on the processor chip, but this approach is yielding diminishing returns. Another approach to decreasing memory latency is to attempt to prefetch data into the cache or caches. There have been a large number of proposed mechanisms for prefetching, and prefetching is employed in numerous computer systems. One common approach is (given a cache fault to a line L(i,j), denoting the ith line in page j) to not only fetch the desired line but to also fetch the next line. In the paper entitled “Special Section on High Performance Memory Systems,” (IEEE Transactions on Computers, Vol. 50, No. 11, November 2001) the paper includes a description of the overall problem and various approaches to its alleviation.
In the prefetching schemes mentioned above and in current prefetching schemes, these schemes operate by observing current access behavior, for example which lines are being fetched, and possibly their relation to other lines currently in the cache.
In the paper entitled “Adaptive Variation of the Transfer Unit in a Storage Hierarchy,” (P. A Franaszek and B. T. Bennett, IBM J. Res. Develop, Vol. 22, No. 4, July 1978, pp. 405-412) the paper discusses a scheme where prefetching in a storage hierarchy is based on information stored in memory on references to individual pages. For example, information is stored and updated which determines, given a fault to a page, whether just the page should be fetched, or the page and a fixed set of other pages should also be fetched. The method in the paper discussed above applies to fetching pages into main memory from disk storage rather than cache lines from main memory.
The prior art prefetching methods do not take into account access pattern behavior useful for improving prefetching performance.
A need therefore exists for improving prefetching performance by storing and updating relevant information on access patterns, as well as software-provided prefetch directives, for each individual page in memory.